| General |
| Supply Voltage | VDD | 2.25 | | 3.63 | V | Note 1 |
| Supply Current (LVPECL, 100 MHz) | IDD | | 50 | | mA | |
| Supply Current (LVDS, 100 MHz) | IDD | | 32 | | mA | |
| Supply Current (HCSL, 100 MHz) | IDD | | 40 | | mA | |
| Standby Current | ISTDBY_ | | 23 | 5 | A | Input pin = STDBY = Asserted (VDD = 3.3V) |
| Frequency Stability | f | | | 20 ppm | | Includes frequency variations due to initial tolerance, temp., and
power supply voltage |
| Frequency Stability | f | | | 25 ppm | | |
| Frequency Stability | f | | | 50 ppm | | |
| Startup Time | tSU | | 5.5 | 6 | ms | From 90% VDD to valid clock output, T = +25C, Note 2 |
| Output Disable Time | tDA | | | 25 | ns | Note 3 |
| Output Enable Time | tEN | | | 6 | ms | |
| Standby Time | STDBY | | | 350 | ns | |
| LVPECL (DSC12x2) |
| Frequency | f0 | 2.5 | | 450 | MHz | |
| Output Logic High | VOH | VDD 1.145 | | | V | RL = 50 |
| Output Logic Low | VOL | | | VDD 1.695 | V | RL = 50 |
| Peak-to-Peak Output Swing | VPP | | 800 | | mV | |
| Single-Ended Output Transition Time (Rise) | tR | | 200 | 250 | ps | 20% to 80%, RL = 50 |
| Single-Ended Output Transition Time (Fall) | tF | | 250 | 300 | ps | 20% to 80%, RL = 50 |
| Output Duty Cycle | SYM | 48 | | 52 | % | |
| Differential Period Jitter RMS | JPER | | 2.0 | | ps | f0 = 156.25 MHz, 10k cycles |
| Differential Period Jitter Peak-to-Peak | JPTP | | 20 | | ps | f0 = 156.25 MHz, 10k cycles |
| Integrated Phase Noise (Random) | JPH | | 0.65 | | psRMS | 12 kHz to 20 MHz @156.25 MHz |
| LVDS (DSC12x3) |
| Frequency | f0 | 2.3 | | 450 | MHz | |
| Output Offset Voltage | VOS | 1.15 | 1.25 | 1.35 | V | R = 100 |
| Differential Peak-to-Peak Output Swing | VPP | 250 | 350 | 450 | mV | |
| Single-Ended Output Transition Time (Rise) | tR | 120 | 170 | 220 | ps | 20% to 80%, RL = 100 |
| Single-Ended Output Transition Time (Fall) | tF | | | | ps | 20% to 80%, RL = 100 |
| Output Duty Cycle | SYM | 48 | | 52 | % | |
| Differential Period Jitter RMS | JPER | | 2.5 | | ps | f0 = 156.25 MHz, 10k cycles |
| Differential Period Jitter Peak-to-Peak | JPTP | | 20 | | ps | f0 = 156.25 MHz, 10k cycles |
| Integrated Phase Noise (Random) | JPH | | 0.65 | | psRMS | 12 kHz to 20 MHz @156.25 MHz |
| Differential Period Jitter RMS (Wide Temp) | JPER | | 3 | | ps | f0 = 156.25 MHz, TA = 40C to +125C |
| Differential Period Jitter Peak-to-Peak (Wide Temp) | JPTP | | 25 | | ps | f0 = 156.25 MHz, TA = 40C to +125C |
| Integrated Phase Noise (Random) (Wide Temp) | JPH | | 0.9 | | psRMS | 12 kHz to 20 MHz @156.25 MHz, TA = 40C to +125C |
| HCSL (DSC12x4) |
| Frequency | f0 | 2.3 | | 450 | MHz | |
| Output Logic High | VOH | 0.64 | | | V | RL = 50 |
| Output Logic Low | VOL | | | 0.1 | V | RL = 50 |
| Peak-to-Peak Output Swing | VPP | | 750 | | mV | |
| Single-Ended Output Transition Time (Rise) | tR | 200 | 260 | 400 | ps | 20% to 80%, RL = 50 |
| Single-Ended Output Transition Time (Fall) | tF | 250 | 370 | 500 | ps | 20% to 80%, RL = 50 |
| Output Duty Cycle | SYM | 48 | | 52 | % | |
| Differential Period Jitter RMS | JPER | | 2 | | ps | f0 = 100.00 MHz, 10k cycles |
| Differential Period Jitter Peak-to-Peak | JPTP | | 16 | | ps | f0 = 100.00 MHz, 10k cycles |
| Integrated Phase Noise (Random) | JPH | | 0.65 | | psRMS | 12 kHz to 20 MHz @100.00 MHz |
| Temperature Specifications |
| Maximum Junction Temperature | TJ | | | +150 | C | |
| Storage Temperature Range | TS | 55 | | +150 | C | |
| Lead Temperature | | | | +260 | C | Soldering, 40s |